1. Field of the Invention
The invention relates to a method for constructing the fault classification tables of analog circuits, and furthermore, to establish the testing tools of the analog circuits by using the functions of computer aided engineering. The constructing method uses failure modes in parts of the analog circuit components, and then applies a circuit simulator to obtain waveform from the defected analog circuit. Exclusive and nonexclusive classification schemes are applied to obtain accurate correspondences between the test data and the failure modes.
2. Description of the Prior Art
As electric technologies go on getting progresses, there are kinds of electric products coming into human's life. However, a great deal of control circuits such as digital and analog circuits are needed to control the operations of the electric products. Everyone should agree that the control circuits can be treated as the souls of the electric products. Therefore, the control circuits must pass many testing procedures before obtaining a required design.
An early testing scheme needs to actually implement the designed circuits after completing the circuit diagram, and perform the testing procedures to the actual circuit for detecting whether the designed circuit achieves the design purpose. When the detecting result is out of expect, the circuit designer must modify the circuit diagram and implement the modified circuit for testing again. The above testing procedure keeps going until the modified circuit achieves the designed requirement. However, this testing procedure wastes many circuit materials, and needs professional circuit engineers to perform this detecting routine. Clearly, it is not an efficient testing scheme.
In order to overcome the disadvantage of the conventional scheme, tools derived from computer aided engineering (CAE) is growing up. The CAE is a computer program established in a workstation or a personal computer. A circuit designer uses graphic icon to build a circuit diagram, and then performs a simulation procedure to the designed circuit by using a simulation package. The simulation package is composed of software modules, which compiles the designed circuit diagram and converts it into circuit modules with wires as connections. The simulation procedure inputs a pulse into the circuit modules, and then calculates the voltages (or current) estimations at each node of the circuit modules. Output waveform generated by the simulation procedure is displayed to the designer when the simulation procedure terminates. The designer can modify the circuit diagram and perform the simulation procedure until the designed circuit achieves his requirement. Of course, the CAE can significantly degrade the time for designing a circuit, and furthermore, can save many circuit materials that are unnecessarily wasted.
Computer aided testing (CAT) is a tool extending the applications of the CAE and simulation to the field of circuit testing. The CAT tools apply failure modes that insert the fault models but the normal models in parts of the circuit components (for example, a fault model simulates the characteristic of a diode acts when punch through appears), and then starts the simulation procedure to record the output waveform as a fault dictionary. Next time when the circuit is testing, the testing result can be compared with the fault dictionary to find the defect components.
In the present days, only the digital CAT tools have been completely developed. However, the characteristics of the analog circuit are quite different with the digital, and thus the analog CAT tools are deficient now. In the prior skills, such as the article "Simulation-based testability analysis and fault diagnosis" disclosed by Sujoy et al. in IEEE Transaction on Autotestcon on September 1996, only a simple classification scheme is suggested to the test points of the analog circuit.
For example, in the FIG. 1A, there are three test points .alpha., .beta., and .gamma., and two failure modes A and B in an analog circuit. In the failure mode B, the measured values (can be voltage or current) obtained from the .alpha., .beta., and .gamma. are 10, 5, and 2, respectively, under the normal condition. In the failure mode A, the measured values of the .alpha., .beta., and .gamma. are respective 10, 6, and 15. The measured values of the .alpha., .beta., and .gamma. are 1, 5, and 7, respectively, while under the failure mode B. However, different failure modes are represented by different fault models of the circuit components, which implies that the measured values will be different while the different failure modes are applied.
Referring to the FIG. 1A, by using the measured values of the .alpha. test point can be recognized the failure mode B from the normal condition but the failure mode A. The normal condition and the failure mode A can be distinguished from the measured values of the .beta. test point. From the measured values of the .gamma. test point, the normal condition, the failure mode A, and the failure mode B can be recognized. The above-mentioned conclusions are listed in FIG. 1B. The fault dictionary listed in FIG. 1C is derived from the method disclosed by Sujoy et al., which is generated based on the concept of "whether the measured values of the test points should be affected by a failure mode". For example, the failure mode A will change the measured values of the .beta. (from 5 to 6) and .gamma. (from 2 to 10) but the .alpha. test point (still keeps in 10). Thus, in the FIG. 1C, the relations between the failure mode A and the test points .beta. and .gamma. are labeled by `.sqroot.`, but the relation between the failure mode A and the test point .alpha. are labeled by a `.times.`. Next time when the analog circuit is tested, the fault dictionary of the FIG. 1C is used to detect whether the analog circuit is normal or not.
Unfortunately, each the testing value is not fixed but varies in a tolerance range that is caused by the environment around the circuit and the defects of the circuit components. For example, the testing value 10 may vary in the tolerance range (8.5, 11.5). However, a larger tolerance range will affect decisions to the measured values.
Furthermore, a fault decision may be done while there are many test points are applied, which will bring troubles to the fault dictionary generated by Sujoy et al. What is clearly needed is a method for constructing the reliable analog CAT tools as to overcome the disadvantages of the conventional skills.